A system-on-chip (SoC) may comprise various sub-systems such as central processing unit (CPU) cores, I/O interfaces, and system logic interfaces. A system clock may be provided to each sub-system, each of which may generate derived clocks from the system clock. Characteristics of the derived clocks such as frequency, skew, and jitter may differ from the characteristics of the system clock. A data transfer device may be provisioned between a pair of sub-systems to transfer data units between the sub-systems.
The data transfer may require high performance and high reliability levels. However, unwanted deviations in the clocks such as jitter and skew may reduce the reliability level at which the data is transferred between the sub-systems. Detecting and responding to the occurrence of excessive jitter may increase the reliability of data transfer between the sub-systems. A jitter detector occupying minimal silicon area may decrease the cost of providing reliable data transfer.